This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Applications No. H11-103272, filed on Apr. 9, 1999, and No. 2000-66263, filed on Mar. 10, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
This invention relates to a dynamic random access memory (DRAM) device and a semiconductor integrated circuit device, and more particularly to an improvement of the refresh operations.
2. Description of the Relates Background Art
For DRAMs, refreshment of memory cell data is indispensable, and it is necessary to refresh data of all memory cells within a predetermined length of time. If refreshment is not effected properly, reading of data will be disabled due to leakage of charges from memory cells.
The time required for refreshment is getting longer and longer as the DRAM capacity increases, and particular consideration has been required about influences of the longer time for refreshment to the performance of DRAM systems. More specifically, although refresh operation of typical DRAM is controlled by a memory controller, or the like, the time spent by the memory controller for issuance of refresh requests increase, and it oppresses the time for the ordinary operation.
As an solution of this problem, there is a method of refreshing a plurality of sub-arrays simultaneously with a single refresh command from the memory controller. With this method, refresh commands from the memory controller can be reduced, and the load to the memory controller can be alleviated. This is a technique that has been employed for years.
On the other hand, for the purpose of improving the performance of a large-capacity DRAM system, a xe2x80x9cmulti-bank systemxe2x80x9d has come to be employed recently. With this system, access time can be reduced substantially by calling interleave operation, which makes an access time and another partly overlap when a plurality of banks are accessed to.
In recent DRAMs, a xe2x80x9cshared sense-amplifier systemxe2x80x9d in which adjacent sub-arrays share a sense-amplifier in order to improve the efficiency per unit area. This system can reduce the area of the sense-amplifier circuit region close to xc2xd of those of systems other than the shared sense-amplifier system.
There has been also proposed a xe2x80x9cnon-independent bank systemxe2x80x9d simultaneously employing the xe2x80x9cmulti-bank systemxe2x80x9d and the xe2x80x9cshared sense-amplifier systemxe2x80x9d (See xe2x80x9cA 1.6 Gigabytes DRAM-with Flexible Mapping Redundancy Technique and Additional Refresh Schemexe2x80x9d, 1999 ISSC digest of technical papers, pp. 410 (ISSN 0193-6530). In this system, adjacent banks are not independent from each other, and share a common sense-amplifier circuit. Thus, advantages of both the multi-bank system and the shared sense-amplifier system can be retained altogether.
However, in case of the non-independent bank system, there is a constraint as a result of using the shared sense-amplifier system, and it is not possible to simultaneously activate two banks sharing a sense-amplifier circuit. Although a shared sense-amplifier circuit can be commonly used by two sub-arrays, while it is used by one of the sub-arrays, it has be disconnected from the other sub-array. This constraint on operation also applies to refresh operation. Also upon activation for refresh operation, in case of sub-arrays sharing a common sense amplifier circuit, unless one of them is set in a precharged state, the other cannot be activated.
The constraint on operation discussed above adversely affects the performance of the DRAM system. For example, when it is desired to start refresh operation of a particular sub-array, if an adjacent sub-array commonly sharing a sense amplifier circuit with the particular sub-array is currently activated, the system has to wait until the adjacent sub-array is set in the precharged state. Further, during ordinary operation, when data of a particular sub-array should be accessed to, in the case where the system is configured to preferentially effectuate refresh operation when a refresh request comes to the adjacent sub-array sharing the common sense amplifier circuit, it is necessary to one precharge the particular sub-array, wait that the adjacent sub-array completes its refresh operation and precharges, and thereafter active the particular sub-array.
According to one aspect of the present invention, a dynamic random access memory device comprises:
a memory cell array which includes a plurality of banks each composed of a plurality of sub-arrays, and sense amplifier circuits shared by sub-arrays in different banks, wherein the sub-arrays make up a plurality of blocks; and
a control circuit which has a row access mode for activating one or more sub-arrays in each bank selected for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank at substantially the same timing to refresh memory cell data therein, wherein the control circuit includes:
a first decoder to which a first address signal and a refresh control signal are inputted, and which outputs a first internal signal which is responsive to the first address signal in the row access mode to select at least one block from the plurality of blocks, and responsive to the refresh control signal in the refresh mode to select all blocks from the plurality of blocks; and
a second decoder to which a second address signal and the first internal signal are inputted, and which outputs a second internal signal which is responsive to the second address signal and the first internal signal in the row access mode to select at least one sub-array in the block selected by the first internal signal, and responsive to the second address signal and the first internal signal in the refresh mode to select all sub-arrays in one bank.
According to another aspect of the present invention, a dynamic random access memory device comprises:
a memory cell array which includes a plurality of banks each composed of a plurality of sub-arrays, and sense amplifier circuit shared among the banks, the sub-arrays in a common bank being arranged sequentially to share the sense amplifier circuit, wherein the memory cell array is divided, for each bank, into a first group composed of a plurality of sub-arrays sharing no sense amplifier within one bank, and a second group composed of a plurality of sub-arrays different from those in the first group sharing no sense amplifier circuit within one bank; and
a control circuit which has a row access mode for activating one or more sub-arrays in each bank selected for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank at substantially the same timing to refresh memory cell data therein, wherein the control circuit includes:
a first decoder to which a first address signal and a refresh control signal are inputted, and which outputs a first internal signal which is responsive to the first address signal in the row access mode to select one sub-array in each bank, and responsive to the first address signal and the refresh control signal in the refresh mode to select sub-arrays of the first group or the second group in each of the banks; and
a second decoder to which a second address signal and the first internal signal are inputted, and which outputs a second internal signal which is responsive to the second address signal and the first internal signal in the row access mode to select at least one sub-array, and responsive to the second address signal and the first internal signal in the refresh mode to select sub-arrays of the first group or the second group in one bank.
According to a further aspect of the present invention, a dynamic random access memory device comprises:
a memory cell array which includes a plurality of block groups, each of which includes a plurality of blocks, each of which includes sub-arrays to make up a plurality of banks, and sense amplifier circuits shared by sub-arrays in different banks; and
a control circuit which has a row access mode for activating one or more sub-arrays in each bank selected for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank at substantially the same timing to refresh memory cell data therein, wherein the control circuit includes:
a first decoder to which a first address signal and a refresh control signal are inputted, and which outputs a first internal signal which is responsive to the first address signal in the row access mode to select one block in each block group, and responsive to the refresh control signal in the refresh mode to select all blocks in each block group; and
a second decoder to which a second address signal and the first internal signal are inputted, and which outputs a second internal signal which is responsive to the second address signal and the first internal signal in the row access mode to select at least one sub-array, and responsive to the second address signal and the first internal signal in the refresh mode to select all sub-arrays in one bank.